PLC Architecture & Scan-Cycle Theory

Engineering

Advanced 120 minutes 2 lessons

PhD-level treatment of Programmable Logic Controller internals: CPU organisation, memory maps, I/O subsystems, the deterministic scan-cycle model, real-time OS scheduling, and the zero-order-hold (ZOH) sampling framework used to design stable discrete-time control loops on PLCs.

Learning Objectives

Describe the hardware architecture of a PLC including CPU, system bus, memory organisation and I/O modules
Derive the relationship between scan period, I/O latency and achievable control bandwidth
Model the PLC scan as a zero-order hold and apply the ZOH frequency-response correction to Bode analysis
Quantify scan-jitter effects and specify maximum scan time for a target closed-loop bandwidth
Apply the Nyquist–Shannon theorem to discrete control via PLC and design appropriate anti-alias pre-filters