Digital Logic & Sequential Circuits — Boolean Algebra to Finite State Machines

Engineering

Advanced 120 minutes 2 lessons

PhD-level digital design: from Boolean algebra and Karnaugh map minimisation through combinational hazards, CMOS gate implementation, D/JK flip-flops, synchronous and asynchronous finite state machines, metastability and clock-domain crossing, with formal verification concepts using temporal logic.

Learning Objectives

Minimise multi-variable Boolean expressions using Karnaugh maps and the Quine–McCluskey algorithm
Identify static and dynamic hazards in combinational logic and design hazard-free implementations
Analyse and design Moore and Mealy finite state machines from state transition diagrams
Apply the D flip-flop excitation equation and state assignment techniques for synchronous sequential design
Evaluate setup time, hold time, and metastability MTBF for synchronous systems and clock-domain crossing