Training PLC Architecture & Scan-Cycle Theory Zero-Order Hold Sampling — Frequency Response & Phase Lag
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Zero-Order Hold Sampling — Frequency Response & Phase Lag

60 min PLC Architecture & Scan-Cycle Theory

Zero-Order Hold Sampling — Frequency Response & Phase Lag

The PLC scan cycle is mathematically equivalent to a zero-order hold (ZOH) sampler: the output is held constant at its last computed value for one scan period $T_s$. The ZOH introduces both gain roll-off and phase lag that must be accounted for in closed-loop stability analysis.

1. The ZOH Transfer Function

In the Laplace domain the ZOH is characterised by:

$$G_{ZOH}(s) = \frac{1-e^{-sT_s}}{s}$$

Converting to the frequency domain ($s = j\omega$):

$$G_{ZOH}(j\omega) = T_s \cdot \text{sinc}\!\left(\frac{\omega T_s}{2\pi}\right) \cdot e^{-j\omega T_s/2}$$

The phase term $e^{-j\omega T_s/2}$ reveals that the ZOH introduces a pure time delay of $T_s/2$ — equivalent to half the scan period. At the process crossover frequency $\omega_c$ this phase lag equals:

$$\phi_{ZOH} = -\frac{\omega_c T_s}{2} \quad \text{(radians)}$$

2. Practical Design Rule

For less than 10° of ZOH-induced phase lag at the crossover frequency:

$$\frac{\omega_c T_s}{2} < \frac{\pi}{18} \quad \Rightarrow \quad T_s < \frac{\pi}{9\,\omega_c} \approx \frac{0.35}{f_c}$$

This is more stringent than the Nyquist criterion ($T_s < 1/2f_c$) and is the working rule for industrial control system design.

3. Scan Jitter & Its Effect on Stability

Real PLCs exhibit scan-time variation (jitter) of $\pm\delta T$ caused by variable communication load and interrupt service routines. Jitter converts to phase uncertainty:

$$\Delta\phi = \omega_c \cdot \delta T$$

For a system with 30° of nominal phase margin, jitter of $\delta T = T_s/10$ at a crossover of $\omega_c = \pi/(9 T_s)$ consumes $\Delta\phi = \pi^2/(90) \approx 11°$ of that margin — leaving only 19°. Jitter reduction via a deterministic RTOS (e.g., VxWorks, QNX) or PROFINET IRT is therefore critical for tight motion control.

4. Anti-Alias Pre-Filter

Aliasing occurs when process signals contain components above $f_s/2 = 1/(2T_s)$. A first-order analog low-pass pre-filter with time constant $\tau_f$ attenuates aliases by:

$$|G_f(j\omega)| = \frac{1}{\sqrt{1+(\omega\tau_f)^2}}$$

Design rule: place the pre-filter pole at $f_f \approx f_c / 5$ to attenuate aliases by at least 14 dB while adding negligible phase at $f_c$.

Worked Example — ZOH Phase Lag Budget

A PID speed loop on a servo drive has crossover $f_c = 20$ Hz. The PLC scan time is $T_s = 4$ ms. ZOH phase lag at crossover:

$$\phi_{ZOH} = -\frac{2\pi \times 20 \times 0.004}{2} = -0.2513\text{ rad} = -14.4°$$

This consumes 14.4° of the typically required 45° phase margin. The designer must either reduce $T_s$ to 2 ms (halving the lag to 7.2°) or redesign the controller with increased gain margin. A 2 ms scan on this PLC requires $T_{exec} < 1.6$ ms — achievable if the program is optimised and the PID loop uses a hardware-accelerated function block. ✓

ZOH Frequency Response Analyser
ZOH phase lag at f_c =?°
Equiv. time delay =?ms
ZOH gain at f_c =?dB

Practice Problems

1. A pressure control loop requires 45° phase margin with crossover at 5 Hz. What maximum scan period $T_s$ limits ZOH lag to 10° at crossover?
2. Derive the ZOH gain roll-off formula $|G_{ZOH}(j\omega)| = T_s |\text{sinc}(\omega T_s / 2\pi)|$ from the Laplace-domain expression $G_{ZOH}(s) = (1-e^{-sT_s})/s$.
3. A PLC exhibits ±0.5 ms scan jitter at a nominal 10 ms scan. If the closed-loop crossover is 8 Hz, how much phase margin is consumed by jitter? Is a 30° nominal margin sufficient?
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